System-on chip (SoC) is a major trend for small form factor, reduced cost, and reduced power solutions which may take full advantage of silicon technologies and integration density. Architectural innovations added with new methodologies and tools for design are posing major challenges for SoC builders. Increased number of Intellectual Property blocks (IPs) are being developed and integrated. For SoCs consisting of tens or hundreds of IP blocks, interconnect architectures is a major challenging task as it directly impacts the wire delays and hence the latency of data across the system. Multi-processing high performance interconnection network schemes are often used in on-chip interconnects. However, using a network-centric approach to integrate multiple heterogeneous and complex SoCs may be beneficial for efficiency, time, and cost purposes. In the network-centric approach the communication may take place in the form of intelligent information and data routed through a switch fabric.
There are many challenges for initiating switch fabric technology paths for sensor data travel in embedded environments. Real-time sensors (commercial, military and medical applications) require fast transport of large amounts of data traveling over considerable distances. Instantaneous conversion of analog sensor data to digital using analog-to-digital reduces latency however may put a significantly larger load on the processor and network. The processing fabric near the sensor may reduce the load on the network which may improve the system performance in terms of latency. Many distributed networks use peer-to-peer protocols which are capable of flattening the hierarchy by use of distributed processing. Today, there is a need to provide chip architecture configurations that intelligently manages the chip's performance and allows it to better meet application requirements.